IGNOU CS-01 ASSIGNMENTS

1(i)

What should be the characteristics of hard disk drive that is to be used for keeping the Airline reservation database? Assume that there is a centralized database that stores the information about all the flight reservations. Give reasons in support of your answer.

 
 
 

For Airline reservation Hard disk has a number of unique features that capitalize upon the
inherent advantages of hard disk and optical storage to offer a self-backing and self-healing storage system which consists of mirrored library systems that appear on the network as a single device.

Redundancy & Clustering

Redundant, fault-tolerant storage is achieved by using clustered data storage and real-timearchiving to optical storage. Clustering technology provides data security by using mirroredmember systems that appear on the network as a single device under one IP address. Clustermembers may be located either in close proximity to one another, or may be distributed across thenetwork for security and logistics concerns, and are capable of real-time mirroring for both thehard disk and optical storage components.

Real-time archiving to optical storage works as an effective data backup method and allows forfile versioning and data rollback functionality. The traditional methods of scheduled backups, ornetwork snapshots, to magnetic tape leave data vulnerable until the actual process is completed.With Good Hard disk, the most current data file versions residing on the optical media canquickly and easily retrieved and restored.

Failover Recovery

During normal operation the Good Hard disk system will monitor network health and will test thepublic, and private, networks for the ability of each member of the cluster to contact oneanother. In the event that a member node in the cluster fails, the surviving member continues toaccept and store information. Once the affected member node has been repaired and brought online,it will connect to the surviving node. The affected node will then discover that the survivingnode had previously failed, and will wait for the acting master to replicate changed data.Because optical storage technology is used for the archive component, the mirrored systems can bequickly re-synchronized by copying only the data that has been added to the surviving member tothe failed member, thus reducing recovery time.

File System Journaling

Data integrity on the hard disk drive-based storage portion of Good Hard disk is indexed usingFile System Journaling, a process which constantly updates, and backs up, the hard disk log filesand recovers unsaved data. This feature ensures that in the event of a system failure, the datatables, links and configurations on the hard disk drive storage prior to the crash can berestored quickly and easily.

UDF File System

Data is written to the optical storage portion of the system using the UDF file system standardwhich was developed to achieve consistency amongst data written to various optical mediums. Thereal world application is that data written to optical media in Good Hard disk can be physicallyexported out of the storage device, and read by popular storage system products on the market today, adding a dimension of instant portability to the solution.

Manageability

Good Hard disk is easily managed using standard browser-based utilities where configuration,storage hierarchy, shares, user quotas and cluster management settings are available from anyInternet-accessible location.
1(ii)

What are the advantages of L1 and L2 Cache memories? Describe the Set Associative Cache mapping scheme.

Cache is a rather generic term. However, the CPU has a bit of memory built into it called L1 Cache which allows it to cache some instructions and data, thus increasing performance (because, from the CPU's point of view, going to RAM is very, very slow).

Also, most modern processors have L2 Cache in the chip, but not in the die itself (like L1). It's a tad slower, but still faster than main RAM.

L1 is usually just like 32-64KB and L2 is 256KB all the way up to like 4MB for some Intel Xeon processors.

Cache Mapping and Associativity

A very important factor in determining the effectiveness of the level 2 cache relates to how the cache is mapped to the system memory. What this means in brief is that there are many different ways to allocate the storage in our cache to the memory addresses it serves. Let's take as an example a system with 512 KB of L2 cache and 64 MB of main memory. The burning question is: how do we decide how to divvy up the 16,384 address lines in our cache amongst the "huge" 64 MB of memory?

There are three different ways that this mapping can generally be done. The choice of mapping technique is so critical to the design that the cache is often named after this choice:

  • Direct Mapped Cache: The simplest way to allocate the cache to the system memory is to determine how many cache lines there are (16,384 in our example) and just chop the system memory into the same number of chunks. Then each chunk gets the use of one cache line. This is called direct mapping. So if we have 64 MB of main memory addresses, each cache line would be shared by 4,096 memory addresses (64 M divided by 16 K).
  • Fully Associative Cache: Instead of hard-allocating cache lines to particular memory locations, it is possible to design the cache so that any line can store the contents of any memory location. This is called fully associative mapping.
  • N-Way Set Associative Cache: "N" here is a number, typically 2, 4, 8 etc. This is a compromise between the direct mapped and fully associative designs. In this case the cache is broken into sets where each set contains "N" cache lines, let's say 4. Then, each memory address is assigned a set, and can be cached in any one of those 4 locations within the set that it is assigned to. In other words, within each set the cache is associative, and thus the name.
    This design means that there are "N" possible places that a given memory location may be in the cache. The tradeoff is that there are "N" times as many memory locations competing for the same "N" lines in the set. Let's suppose in our example that we are using a 4-way set associative cache. So instead of a single block of 16,384 lines, we have 4,096 sets with 4 lines in each. Each of these sets is shared by 16,384 memory addresses (64 M divided by 4 K) instead of 4,096 addresses as in the case of the direct mapped cache. So there is more to share (4 lines instead of 1) but more addresses sharing it (16,384 instead of 4,096).

Conceptually, the direct mapped and fully associative caches are just "special cases" of the N-way set associative cache. You can set "N" to 1 to make a "1-way" set associative cache. If you do this, then there is only one line per set, which is the same as a direct mapped cache because each memory address is back to pointing to only one possible cache location. On the other hand, suppose you make "N" really large; say, you set "N" to be equal to the number of lines in the cache (16,384 in our example). If you do this, then you only have one set, containing all of the cache lines, and every memory location points to that huge set. This means that any memory address can be in any line, and you are back to a fully associative cache.

(http://www.pcguide.com/ref/mbsys/cache/funcMapping-c.html)
1(iii)
What happens when Multiple Interrupt occurs simultaneously? What is an Interrupt Vector? How are the interrupt recognised in micro-Computers?
   
1(iv)

What is the need of Input/ Output Processor? How does an I/O processor support the Input-Output? Compare and contrast I/O Processor to Direct Memory Access (DMA).

   
2(i)

Show step by step multiplication of the values –16 with +12 after converting them to binary, using Booths algorithm. Indicate details of sizes of the registers used.

   
2(ii)
Express the following numbers in IEEE 32-bit floating-point number format.
    • –226.00125 × 10 -20
    • 0.000875 × 10 10
    • 0.0
   
2(iii)
What are the different addressing modes in 8086 microprocessor, which allow efficient addressing of arrays? Justify your answer and give suitable examples. Which of the available addressing mode in this processor is best suited for subroutine calls? Explain with the help of an example.
   
2(iv)
A hypothetical machine has 32 registers, 50 operation codes and 5 addressing modes. Design a suitable microinstruction format for such a machine. Describe the execution of an Instruction using the microinstructions designed by you for such machine. Make suitable assumptions, if any.
   
3(i)

A Computer System is to be used for processing the visual data received from space craft. What should be the architecture of such a Computer? (You must describe about the Processor type, any typical processing requirements, type of memory, type of instructions, type of registers, type of addressing modes, etc.).

   
3(ii)
A computer just needs 32 to 64 general purpose computers, whereas the Reduced Instruction Set Computers (RISC) has large number of registers; what may be the use of such registers? Justify your answer. Why cannot these registers be replaced by Cache memory?
   
3(iii)
 Compare and contrast various Multiprocessor Organisations?
   
3(iv)
What is Cache Coherence problem? Describe the problems relating to concurrent processes execution in Multiprocessor systems.